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Reset Deassertion Metastability

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musashi1029

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Hi experts,

I have a register whose async reset is not synchronized for deassertion. When I deassert reset for this register, will metastability occur if the D input is same as the current Q pin? (I.e., write enable is low for this register)

May I omit the synchronizer in this case?
 

Hi experts,

I have a register whose async reset is not synchronized for deassertion. When I deassert reset for this register, will metastability occur if the D input is same as the current Q pin? (I.e., write enable is low for this register)

May I omit the synchronizer in this case?
do you mean it is a constant? in that case you do not need to infer a register.
do you mean write can occur occasionally? in that case just synchronise the reset.
 

If D and Q are already in the L / 0 state then there's no change to
be made in the latch guts. You could assess this yourself using a
SPICE / Spectre / xxx analog simulator and transistor level latch
circuit, slide the data past the clock in transient analysis and look
for any hint that a Q-flip might be possible. Then run with the
opposite setup and see where metastability blows out the Tpd
and then flips over.

This would let you prove that the logic simulation is giving you
bogus direction / outcomes. But then what? The Methodology
Harpies will still want to eat your liver, only for showing them
as fools.

Now if the reset was registered on the way in, why is it not, on
the way out? Maybe there's a simple solution to this non-problem.
 

do you mean it is a constant? in that case you do not need to infer a register.
do you mean write can occur occasionally? in that case just synchronise the reset.
Hi kaz1,

No, it’s not a constant. It’s sometimes written, but the write enable is low for some time after reset. I know it’s always safe to sync reset deassertion, but wanted to understand what would happen if it was not done.

If D and Q are already in the L / 0 state then there's no change to
be made in the latch guts.
Hi dick_freebird,

Thanks for the answer, but let me confirm for sure.
Even if reset is deasserting around the clock egde, if the D-pin is stable, Q is not affected?
 

The requirement is D = O, so that Q doesn't change on the next clock edge after reset deassertion. Otherwise multiple FF might toggle at different clock edges, possible generating an illegal state or unexpected bit combination.
 

Hi kaz1,

No, it’s not a constant. It’s sometimes written, but the write enable is low for some time after reset. I know it’s always safe to sync reset deassertion, but wanted to understand what would happen if it was not done.
Well I do a lot of clock crossings without worry whenever my signals are sampled long time after being driven.

I believe same applies to reset release. if you know data is written to register well after reset release then I wouldn't worry. (semi-static).
 

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