Hi,maxsnail said:vcs doest support TCL, I cant live without TCL,
though I did not compare them, but I think VCS is do more optimize for speed,
Well that's certainly not true. For instance one can perfectly simulate:Thomson said:NC-verilog is a cycle-driven based simulator, so if your design is a totally synchronous logic then your performace against VCS will be obtained.
mmazio said:If you use Synopsys DC, the only choice for simulator is VCS.
For RTL debugging, I think NC is better than VCS. But Debussy is a good plus for VCS. The RTL simulation performance of the two if almost the same.
maxsnail said:vcs doest support TCL, I cant live without TCL,
though I did not compare them, but I think VCS is do more optimize for speed,
repac said:maxsnail said:vcs doest support TCL, I cant live without TCL,
though I did not compare them, but I think VCS is do more optimize for speed,
nc-verilog supports good TCL interface....
i have successfully use TCL interface of NC to do simulation flow control and some simple result check.
If you are TCL user , i think you will like NC.
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