Which simulation tool is better, VCS 7.0 or NC-Verilog 5.4 ?

[toolgread]

VCS7.0 VS. NC-Verilog5.4

ncverilog because sign-off need it

 

[pookey]

VCS7.0 VS. NC-Verilog5.4

my test result.

ncverilog version: 5.4s04
vcs version: 7.1.2

ncverilog run time: 2:08
vcs run time: 2:26

ncverilog faster then vcs.

 

[aji_vlsi]

Re: VCS7.0 VS. NC-Verilog5.4

my test result.

ncverilog version: 5.4s04
vcs version: 7.1.2

VCS 7.1.2 --> Close to 1 year old release, comparison results may be skewed unless you use latest versions of any tools under compariosn.

Just MHO
Aji

 

[pookey]

VCS7.0 VS. NC-Verilog5.4

sometimes vcs v7.2 crach on RHEL3 platform,so I back to v7.1.2
vcs v7.1.2 stable but code coverage function crach.

 

[nanako]

Re: VCS7.0 VS. NC-Verilog5.4

the latest version for the 2 camps are

IUS 5.5 -- released few days ago
VCS 7.2 -- should be releasing a newer version either this month or next month.

Added after 3 minutes:

my test result.

ncverilog version: 5.4s04
vcs version: 7.1.2

ncverilog run time: 2:08
vcs run time: 2:26

ncverilog faster then vcs.

the simulation time depends on various factors like the size of the design, the coding style of the design and the usage of the tools (switches)

i know for vcs there are switches you could play with to make the simulation run faster like switching to 2states only.

so it would be a fair comparison if you use the tools to its optimal setting to get the best result from it.