Which is more closer to real time scenario "negedge clk" or "posedge clk" testbench?
Hi All,
I am having a query. MY RTL works on "posedge clk" and MY Test Bench works on "negedge clk" I want to know If I run my test Bench on "posedge clk" which is more closer to real time scenario "negedge clk" test Bench or "posedge clk" test bench.
I am having a query. MY RTL works on "posedge clk" and MY Test Bench works on "negedge clk" I want to know If I run my test Bench on "posedge clk" which is more closer to real time scenario "negedge clk" test Bench or "posedge clk" test bench.
Use same posedge clk with 1ns delay on signals you are driving and take signals after 1ns delay .
with this delay u should not see any issue if so then there is a prob with RTL .
úsing positive or negative clock should not matter for rtl simulation.
but u should use posedge (or clock edge used in application scenario) for gatelevel netlist simulation where u will back annotate timing information.
I am Having a Master which do AXI transactions. Master do transactions on "negedge" and my "rtl" works on "posedge" . I mean it accepts data at "posedge" of data. Will it make any effect to "rtl" verification.