[SOLVED] [Design Compiler] How to compile a design with posedge and negedge clk?

[Zackery]

hi, i am tring to compile a sram module from sky company, but the RTL codes has two clk(i dont know how to describe this situation), like the picture below, it has both posedge and negedge clk's always block,

i compile as normal, same as the design with one clk edge, but it seems the tools think it has one edge clk:

how can i change the command or what should I add in the tcl?

 

[barry]

the problem is not that you’re using two clock edges.READ THE ERROR MESSAGE!! You’re driving dout from two sources ( in two different blocks)

 

[Zackery]

the problem is not that you’re using two clock edges.READ THE ERROR MESSAGE!! You’re driving dout from two sources ( in two different blocks)

Thanks, i have noticed that, the dout are in two always block. According to the case I inquired from the some websites, a signal cannot be driven in two always blocks, but their cases have the same clock edge in two always blocks, so I will ask whether the "DC does not recognize two kinds of clock edges" caused by different clock edges. And the most important is that the code is got from skywater PDK, so i dont know whether changes in it is a good choise.

 

[barry]

Again,

THE PROBLEM IS NOT THAT YOU HAVE TWO CLOCK EDGES

The problem is you're driving a signal from two different sources.

 

[FvM]

As clearly shown by the delay statements, it's a simulation model, not code intended for synthesis. You shouldn't expect that it's synthesizable.

 

[Zackery]

Again,

THE PROBLEM IS NOT THAT YOU HAVE TWO CLOCK EDGES

The problem is you're driving a signal from two different sources.

Ok，many thanks