I wonder what to do if the post layout timing analysis not matching to the synthesis results. The synthesis results met all the timings but the post layout timing doesn't meet. Besides solving all conjestion problems, there seems no valid means on the layout side. What else can I do?
Re: What to do if post layout timing not matching to synthes
Pre-route and post-route will check differently. synthsis meet doesn't mean meet in post-route. some path only be checked in Post-route, unless you modify some default option when synthsis. ideal clock and CTS are also differently.
re-route manually,
re-synthesis with enough margin,
replace some hi-Vt cell with low-Vt cells
remove some secondary-level power-gating logic
adjust floorplan, change congestion target
change area target.
even considering re-coding the rtl ...
Re: What to do if post layout timing not matching to synthes
I agree with what stevepre and au_sun said and this is what we've practised. But one thing I am not sure: after many tries, how to tell that the P&R tool cannot make it so that refloorplanning, resynthesis or re-coding is needed. I guess I lack experience to make judgement here but only to try more possibilities.
Re: What to do if post layout timing not matching to synthes
for setup time violation, your can refloorplan or resynthesis or skew
clock edge intentionally to generate some useful skew to extend
clock cycle in timing critical path. for hold time violation, you can add
delay cell in problem path to eliminate the problem.
best regards
steven852 said:
I wonder what to do if the post layout timing analysis not matching to the synthesis results. The synthesis results met all the timings but the post layout timing doesn't meet. Besides solving all conjestion problems, there seems no valid means on the layout side. What else can I do?