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It's the method to combine (each) 2 drains of 2 parallel FETs (or drain and source of 2 serial FETs) in order to save layout space. See this **broken link removed**.ramesh441 said:Can anyone say what is transistor chaining? How to do it in Cadence Virtuoso-XL .
ramesh441 said:My DRC errors are
"Maximum N+ DIFFUSION to the nearest P= pick-up spacing (inside P-WELL or T-WELL) is 20um (I/0, RAM, ROM, capacitor and diode are expected)"
.