What is transistor Chaining?

[ramesh441]

Can anyone say what is transistor chaining?

How to do it in Cadence Virtuoso-XL .

I tried it but I couldn't do it

 

[erikl]

Can anyone say what is transistor chaining? How to do it in Cadence Virtuoso-XL .

It's the method to combine (each) 2 drains of 2 parallel FETs (or drain and source of 2 serial FETs) in order to save layout space. See this **broken link removed**.

 

[ramesh441]

I did in the same way but I am getting some DRC errors(in Calibre) regarding this.


What the "transistor Chaining " option in Virtuoso-XL do???
when I select did it there is change in my transistor structure??

Can you say me how to use the option in Virtuoso-XL

 

[deepak242003]

what error you are getting ramesh....can u post few of them?

 

[ramesh441]

My DRC errors are

"Maximum N+ DIFFUSION to the nearest P= pick-up spacing (inside P-WELL or T-WELL) is 20um (I/0, RAM, ROM, capacitor and diode are expected)"


What I have done is just placed one transistor over other i.e I chained them (If DGS is structre of M1 and SDG is of M2 , I just placed S (source) of M1 on S of M2).

This is the only error I am getting when I am running with Calibre.

 

[deepak242003]

My DRC errors are

"Maximum N+ DIFFUSION to the nearest P= pick-up spacing (inside P-WELL or T-WELL) is 20um (I/0, RAM, ROM, capacitor and diode are expected)"
.

This is latchup up prone error.. You might not have added substrate connection for your transistor... Add proper substrate connection , ntap here , and this error will b gone.

Dont forget to press help me button

-Deepak.

Added after 52 seconds:

dont forget to connect ntap to ground

gudluck.