In order to model the wires we use a concept called as Wireload model in Synthesis..So wireload model is something which calculates the net delay based on the fanout of a particular gate..Basically its a statistical based model which gives the prelayout estimation
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cell delay and net delay is used to caculate the timing of circuit , here WLM is used to caculate the net delay value, in design flow, different WLBs will be used in different stages.