what do pipeline AD use for delay element

[iexplorer]

I have seen so many types ,like use C2MOS,dff,I try c2mos , however, when output is low , it can not hold for the full hold clock to make the ouput wrong,how can I deal with it ? Only edge DFF can give me exactly correct code?

 

[A.Anand Srinivasan]

Sample and hold is being used as delay element.... the MOS take care that the leakage current is too low.... you have bottom plate sampling and bootstrapping techniques.....

 

[hr_rezaee]

Hi
If do you mean digital signal answer is DFF
if analog signals answer is S/H.
regards

 

[bbbb]

Hi DFF not necessary. Use a simple latch (two inverters + two switches as given in every digital design book) . Remember using non overlapping clocks for different latches.