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what do pipeline AD use for delay element

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iexplorer

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I have seen so many types ,like use C2MOS,dff,I try c2mos , however, when output is low , it can not hold for the full hold clock to make the ouput wrong,how can I deal with it ? Only edge DFF can give me exactly correct code?
 

A.Anand Srinivasan

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Sample and hold is being used as delay element.... the MOS take care that the leakage current is too low.... you have bottom plate sampling and bootstrapping techniques.....
 

hr_rezaee

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Hi
If do you mean digital signal answer is DFF
if analog signals answer is S/H.
regards
 

bbbb

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Hi DFF not necessary. Use a simple latch (two inverters + two switches as given in every digital design book) . Remember using non overlapping clocks for different latches.
 

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