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In analyzing the speed performance of a synchronous circuit, what design corners should be checked based on the factors listed to ensure the design will operate within a specified range of operating conditions.
normally, without OCV. we need to check setup with wcl-worst_case_low or wcz-worst_case_zero and with hold, we check bc-best_case or ml-max_leakage.
ofcourse,when signoff, we need OCV check with many corner included.
for synthesis, we just be careful with setup check (hold check will done at PnR)
1- synthesis should be done with the worst corner(s) to reach the setup constraints.
2- place & route, I usefully have in MMMC flow, how many setup condition, where I want to be sure my design must reach the setup constraints, and for the hold condition, all corners I want to have my design to be functional. I mean, some corners do not have a specific setup condition, but I want to be sure the chip works properly.
3- STA, I checks setup & hold, in all corners used before with the three RC extractions.