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NMOS and PMOS are defined by the gate lenght and width . the smallest gate length available in the library cells determines the technology .. For example the min gate length for a perticular Library is 65 nm .. then it catagorized as 65nm technolog.
it means
half of the length of the transistor=65nm
less the size more the density
i think u herd that 65nm and 85nm from FPGA
altera Stratix 3 is of 65 nm technology
means the transistor which can be used in that fpga is of the length(half) of 65 nm
Length means distance between source and drain
generally a vlsi chip is measured with the technology used to manufacture it,,, and this technology name comes from the gate length of the smallest transistor used in the chip and generally techlogy enhances the gate size decreases ,,,it could be 65nm r 90nm ,,nm is nanometer
Added after 8 minutes:
actually it is the half the gate length of a smallest transistor
it depends upon given data
it is nanao meter
about ic sizing
some times it is source to drain
and some times complete inverter circuit of mosfet
and sometimes complete circuit of ic
hey ...in some of the above posts...ppl saying ....65 nm is "HALF" the channel length(i.e equal to Feature size)....whereas some saying its the channel length(tht means must be twice the Feature size)......
can someone clarify....watz the actual answer...as far as i m aware its the Lmin n not feature size(of course it can even be referenced wrt Feature size)
1.What is the difference beween 90nm design flow and 130nm design flows.
please help me find answer to this.
Because as far i know as the technology shrinking Signal integrity effects(like crosstalk,EM,Antenna) come into picuture.
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