Sign-Off MMMC setup in 65nm CMOS

[shlooky]

Hi there!

I will be taping out my first design in 65 nm CMOS technology. I would like to discuss the LIB corner + RC corner combination for setup/hold time checks in PnR.

From what I gathered, in 65 nm I do not have to worry about temperature inversion, so setup checks should be just worst-case PVT lib + Cmax / RCmax at high temperature...

Setup Checks:
1. (Slow transistors, 0.9*VDD, 125C) + (RCmax / Cmax @ 125C) = 2 corners


Hold time checks are the part I am afraid of.... Could you guys please suggest the correct combination for this technology?
So far, I got the obvious combination of best-case PVT lib + all C/RC corners at low temperature... The second one is suggested by the foundry. Can you please explain its purpose?

Hold Checks:
1. (Fast transistors, 1.1*VDD, -40C) + (Cmin / Cmax / RCmin / RCmax @ -40C) = 4 corners
2. (Slow transistors, 0.9*VDD, 125C) + (Cmin / Cmax / RCmin / RCmax @ 125C) = 4 corners

The foundry also suggests 10% derating of clock paths.

Am I missing something else? What settings would you recommend?
Thanks in advance, guys!

Shlooky

 

[oratie]

For example, you have two clock paths. Delay of them consist of buffs/invs delay plus wire delay. Total delay of both path are equal in one corner. Are you sure that wire lendth of both path are equal? Are you sure that number of cells in both path are equal? If not - in different corners the total delay may not be equal. So, you may get non-zero clock skew (it may be bad for setup or hold).

And, of course, the best starting point for beginners is the foundry recomendation for signoff STA.

 

[ThisIsNotSam]

you have so few corners in 65nm that you should just be checking all of them. this is what my team has done in the past half a dozen 65nm chips we did. The additional run time of the tools is tiny.

temperature inversion does exist in 65nm technology, don't be so fast to rule it out.

 

[shlooky]

you have so few corners in 65nm that you should just be checking all of them. this is what my team has done in the past half a dozen 65nm chips we did. The additional run time of the tools is tiny.

temperature inversion does exist in 65nm technology, don't be so fast to rule it out.

Hi there,

The foundry provided only LIB with SS transistors, 0.9*VDD, 125C and they also recommend to use this one for setup checks.

LIBS with SS transistors , -40C and also 125C are available with 0.6*VDD. I assume that temp. inversion is present only with such a low VDD. Plus, my design will not be used in such conditions...

How about hold uncertainty in SDC, guys? How much of a hold time margin is reasonable?

Thank you!

Shlooky

 

[ThisIsNotSam]

Hold time uncertainty is usually very small, no more than tens of picoseconds. In the absence of clear recommendation from the foundry, that is.

 

[shlooky]

Hi guys,

Thank you very much for your insight and help....

One last question, I hope

I know this is not strictly related to 65nm, but rather a general question... How much of "hurtful" clock skew is tolerable during CTS? The value I started with is 5% of clock period.

Thanks
Shlooky

 

[ThisIsNotSam]

what is it that you call 'hurtful' skew?

 

[shlooky]

I meant normal "clock skew" which is not intentionally inserted by the EDA tool as "useful" during CTS and timing.

 

[ThisIsNotSam]

Hard to say. We have had designs where performance was more important than anything else, so skew was allowed to be infinite. We have had designs where the nominal clock period was 1.0ns but some paths were as long as 1.5ns due to useful skew. You pay a penalty, naturally, as the clock tree becomes more complicated and hold problems may appear more often.