Verilog2001 $signed question

[davyzhu]

Hi all,

How can I multiply a signed operand with a unsigned operand?

input [7:0] a;
input signed [7:0] b;
output signed [15:0] z;

assign z = $signed({1'b0,a}) * b;

or

assign z = $signed(a) * b;

And why?

Thanks!
Davy

 

[zhaoyimiao]

the first one is correct, if a[7] can be sign bit the second one is also ok.

 

[steven852]

Without $signed(a), the result z will be $unsigned even though b is signed.