How to multiply a fixed-point number by a signed integer number in Verilog

[mohamis288]

I want to multiply an 8-bit fixed-point number by an 8-bit signed integer number in Verilog and we want to have just 8 bits in output. So we want to round our output so that after multiplication, our output must be a signed integer. Unless it will overflow. How can I do that?

Wire [7:0] b0 = 8b'0_0100100;
Input [7:0] input = 8b'10100100;
Assign mul= b0*input;

Is it correct?

 

[barry]

1) Unless you have some severe constraints, you’re going to have a lot of opportunity for overflow.
2) What’s your fixed point format, 4.4? 6.2?
3) You’ll probably need to do rounding, unless you can live with the truncation error.
4) Im not a verilog person, so I can’t speak to that, but I don’t think your simplistic “b0*input” will work. I think you need to convert both numbers to the same type.

 

[FvM]

Your variables are actually unsigned, signed has to be declared explicitly. Whe multiplying unsigned with signed, the unsigned variable is treated as signed, thus you need to extend 8 bit unsigned coefficient to 9 bit signed.