Verifying An Address Held in a Shift Register

[Endymion]

I have a program in VHDL that has a 16-bit shift register, a bit counter and a simple FSM. The bit counter counts down from 15. When the carry out is 1, we know we've reached 0 i.e. we've shifted in 16 bits.

At this stage, I'd like to verify that the shifted in address is the same as an internal constant. My question is, do I pass this shifted in data to the FSM for verification? As of right now, the FSM only has two states:

IDLE -> Address.

If I shift in the address, I can add in a 'address verification' stage and then shift in the data.

IDLE -> ADDRESS -> VERIFY ADDRESS -> SHIFT IN DATA

If the address isn't OK, the FSM returns to IDLE. Essentially, I'm trying to design a simple protocol over SPI that allows a uC to shift in (or shift out) data to various devices based on their internal address. I only want the data/commands to go the device whose being addressed.

Note: I know I can use Chip Select, that's what its meant for. However, I'd prefer using addresses. This is because the devices can be on different PCBs and I can't send a large number of CS lines over. Therefore, using addresses is something I'd prefer.

 

[barry]

Personally, I'd do what you suggest (adding another state). Or, you could set a flag when you exit the Address state, indicating you've acquired a complete address; then, another process (FSM) could monitor the flag and when it gets set, it would do the compare. I don't see any advantage to the second method, though.

Your 'verify address' could also be a comparator (external to the FSM) that constantly looks at the shift register and sets a flag when the compare is true. Then your FSM would look at the 'compare' flag when it exits the address state to determine where to go next.

Lots of ways of doing this...

 

[BlackHelicopter]

Depending on how you decide to program it you could add an extra "verify addr" state in the FSM and do it that way, or add a comparator to the datapath which will compare the output of the shift register to the internal constant and generate a control signal (comparator output) for the FSM to determine what state to go to next.