#### dpaul

##### Advanced Member level 5

I have implemented the CRC-16-CCITT (x^16 + x^12 + x^5 + 1) with Normal Polynomial 0x1021 and Initial value = x"FFFF".

I have implemented the VHDL function in a package file as shown below.

Code:

```
-- CRC16 function
function f_crc16_ccitt_d8 (
data_in : std_logic_vector(7 downto 0); -- Input byte data
crc_in : std_logic_vector(15 downto 0)) -- Input 16 bit CRC from initial/prev stage
return std_logic_vector is -- Return the final 16 bit CRC
variable d: std_logic_vector(7 downto 0);
variable c: std_logic_vector(15 downto 0);
variable newcrc: std_logic_vector(15 downto 0);
begin
d := data_in;
c := crc_in;
newcrc(0) := d(4) xor d(0) xor c(8) xor c(12);
newcrc(1) := d(5) xor d(1) xor c(9) xor c(13);
newcrc(2) := d(6) xor d(2) xor c(10) xor c(14);
newcrc(3) := d(7) xor d(3) xor c(11) xor c(15);
newcrc(4) := d(4) xor c(12);
newcrc(5) := d(5) xor d(4) xor d(0) xor c(8) xor c(12) xor c(13);
newcrc(6) := d(6) xor d(5) xor d(1) xor c(9) xor c(13) xor c(14);
newcrc(7) := d(7) xor d(6) xor d(2) xor c(10) xor c(14) xor c(15);
newcrc(8) := d(7) xor d(3) xor c(0) xor c(11) xor c(15);
newcrc(9) := d(4) xor c(1) xor c(12);
newcrc(10) := d(5) xor c(2) xor c(13);
newcrc(11) := d(6) xor c(3) xor c(14);
newcrc(12) := d(7) xor d(4) xor d(0) xor c(4) xor c(8) xor c(12) xor c(15);
newcrc(13) := d(5) xor d(1) xor c(5) xor c(9) xor c(13);
newcrc(14) := d(6) xor d(2) xor c(6) xor c(10) xor c(14);
newcrc(15) := d(7) xor d(3) xor c(7) xor c(11) xor c(15);
return newcrc;
end function f_crc16_ccitt_d8;
```

The function takes a byte and the initial/previous CRC value (if the input byte is the 1st byte then crc input = 0xFFFF) as inputs and returns the 16 bit calculated CRC value.

I am calculating the CRC for a 11 byte data, i.e. a loop running 11 times calls this function and calculates the final CRC.

Now the above is done in hardware, at the FPGA. The frame data (11 bytes data + 16 bits CRC) is received from the processor where a firmware calculates the CRC and sends it along with trhe data. My design at the FPGA re-calc the CRC from the data received. My calc CRC and the one received should match.

Current situation is that they are not matching!

**I want to know how can I verify this calc for CRC-16-CCITT, without doing the calc manually by hand? What are my options?**