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[SOLVED] Why "The Memory Controller has one address channel?"

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zzzhhh

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This is a sentence in section "Arbitration in AXI Shim" of Xilinx's "Zynq-7000 SoC and 7 Series FPGAs MIS v4.2 100 (UG586)" document (page 101): "The Memory Controller has one address channel."

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But I double checked the MIG core I inserted into the block design of Vivado, the slave AXI interface on the MIG core does have both read and write address channels (coming from AXI SmartConnect). So, why does the document claim that the MIG core has only one address channel, and what does arbitration mean if I have both read and write address channels (and what arbitration option I should choose)?
 

Probably here the "one address channel" means the connection b/w the MIG core and the physical memory chip. You have only one address bus there.

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