I am trying to include AMS pads (process AMS C35B3C3) in my layout but I am getting the BAD_SUBSTR_SUBTAP_FLOAT_ERC error when running Assura DRC. Regarding the pins, I am using the PIN PAD layer and I am naming the power and ground pins "vdd3r!" and "gnd3r!", respectively.
The pad AGND3ALLP is connected to gnd! via the PIN PAD layer. This way, and with the connection of AVDD3ALLP, I assume that all the rest of the pads are correctly biased.
PAD pin would connect to the explicit pad opening, the signal
(maybe it is a ground in this case). But there may be protection
circuitry, guardrings etc. which have their own pins distinct from
the pad opening and one of which may need to be assigned the
substrate connection.
That, in the end, the two become electrically identical may not
be understood by ERC/SRC at the level you're working on.
PAD pin would connect to the explicit pad opening, the signal
(maybe it is a ground in this case). But there may be protection
circuitry, guardrings etc. which have their own pins distinct from
the pad opening and one of which may need to be assigned the
substrate connection.
That, in the end, the two become electrically identical may not
be understood by ERC/SRC at the level you're working on.
You need to look at the guts. Standard cell I/Os
often carry "stuff" like distributed ESD clamp
elements, and any of those actives probably have
substrate terminals as a capacitive parasitics return,
if not an ohmic connection. Look at the symbol and
instance properties, the schematic view of the pad,
etc.