jianhuachews
Member level 2
Hi can anyone provide me vhdl codes for divide by 50 frequency divider circuit using flip-flops?
Thanks in adv.
Thanks in adv.
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if (cnt = 1) then
cnt <= HALF_TC;
out_sig <= not out_sig;
else
cnt <= cnt - 1;
end if;
if( rising_edge(Clk) ) then
if(counter < divide/2-1) then
counter <= counter + 1;
output_clk <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
output_clk <= '1';
else
output_clk <= '0';
counter <= 0;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lab3C is port(
Clk, nreset: in std_logic;
output_clk : out std_logic;
divide_value : in integer
);
end ;
architecture Behavior of lab3C is
signal counter,divide : integer := 0;
begin
divide <= divide_value;
process(Clk,nreset)
begin
if (nreset = '0') then
output_clk <= '1';
counter <= 0;
elsif( rising_edge(Clk) ) then
if(counter < divide/2-1) then
counter <= counter + 1;
output_clk <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
output_clk <= '1';
else
output_clk <= '0';
counter <= 0;
end if;
end if;
end process;
end ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lab3cTB is
end;
architecture behavior of lab3cTB is
signal clk,output_clk,nreset : std_logic;
signal divide_value : integer;
constant clk_period : time := 10 ns;
begin
-- Component Instantiation
uut: entity work.lab3C PORT MAP(
clk => clk,
output_clk => output_clk,
nreset => nreset,
divide_value => divide_value );
simulate : process
begin
divide_value <= 50;
wait for 500 ns;
wait;
end process;
clk_process : process --generates a 100 MHz clock.
begin
nreset <= '0';
wait for clk_period;
nreset <= '1';
wait for clk_period;
clk <= '0';
wait for clk_period/2; --for 5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 5 ns signal is '1'.
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lab3d is port(
Clk: in std_logic;
output_clk : out std_logic;
divide_value : in integer
);
end ;
architecture Behavior of lab3d is
[B][COLOR="#FF0000"]
signal counter,divide : integer := 0;[/COLOR][/B]
begin
divide <= divide_value;
process(Clk)
begin
if( rising_edge(Clk) ) then
if(counter < divide/2-1) then
counter <= counter + 1;
output_clk <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
output_clk <= '1';
else
counter <= 0;
output_clk <= '0';
end if;
end if;
end process;
end ;
generic (DivideValue : integer := 25000000);
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity sec_clk is
Port (
Clk : in std_logic;
op : out std_logic
);
end sec_clk;
architecture RTC of sec_clk is
[COLOR="#FF0000"] constant max_count : natural := 25000000;[/COLOR]
begin
compteur : process(Clk)
[COLOR="#FFA07A"] variable count : natural range 0 to max_count;[/COLOR]
begin
if rising_edge(Clk) then
if count < max_count/2 then
op <='1';
count := count + 1;
elsif count < max_count then
op <='0';
count := count + 1;
else
count := 0;
op <='1';
end if;
end if;
end process compteur;
end RTC;
max_count : natural := 25000000;(this line of your code defines for 1hz from 25000000 if it will repeat again it will becomes 2hz from 50000000)