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8 phases non-overlapping clock from johnson by 4 divider

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Anomis

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Hi EDA members,
I want to design a 8 phases non-overlapping circuit from johnson divider by 4 circuit. I already referred to this post for a hint:
But the thing is my clock input has constraints that I cannot make it as large as i want:
For example I have a source of fi=4 GHz and want 8 phases output signals with DCD = 12.5 % non-overlapping, f0=1GHz. The simple solution is just to use a divider by 8 circuit with fi=8GHz, then i have f0 = 1GHz with 8 phases as desired. However i don't have such big clock source of 8GHz. How can I solve this problem with this condition?
Very much appreciated your help!
Tommy
 

BradtheRad

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Build a 3-bit counter. This can be done by adding two divide-by-2 flip-flops after the clock.
Clock speed 1 GHz.
Feed the 3 bits to a 1-of-8 decoder IC (with 3 input pins).
In binary this yields 8 possible values. Thus it selects one of 8 output pins.
State changes at same rate as clock.

A search for 1-of-8 selector IC turns up these candidates:
4512
74138
74151
74152

--------------------------------------------

4017 IC (decade counter) does the job but can't manage the speed you specify.
 

barry

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Build a 3-bit counter. This can be done by adding two divide-by-2 flip-flops after the clock.
Clock speed 1 GHz.
Feed the 3 bits to a 1-of-8 decoder IC (with 3 input pins).
In binary this yields 8 possible values. Thus it selects one of 8 output pins.
State changes at same rate as clock.

A search for 1-of-8 selector IC turns up these candidates:
4512
74138
74151
74152

--------------------------------------------

4017 IC (decade counter) does the job but can't manage the speed you specify.
I don't think any of those selectors you suggest will work anywhere near 1 GHz. I think this 1GHz requirement is going to limit the solution to ECL or similar technology.
 

dick_freebird

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At 4GHz the nonoverlap logic may be hard pressed to
do the job. Gating the output bit with clock will make a
lot of spikes. Probably at least have to delay-compensate
the clock image that's fed to the phase logic to keep from
losing too much pulse width or allowing glitches through,
in the nonoverlap logic. Might be best to make an edge
detector off CLK and use it to re-register CLK, Q0, Q1
broadside (those signals, perhaps being "lagged" to get
robust capture).
 

Anomis

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At 4GHz the nonoverlap logic may be hard pressed to
do the job. Gating the output bit with clock will make a
lot of spikes. Probably at least have to delay-compensate
the clock image that's fed to the phase logic to keep from
losing too much pulse width or allowing glitches through,
in the nonoverlap logic. Might be best to make an edge
detector off CLK and use it to re-register CLK, Q0, Q1
broadside (those signals, perhaps being "lagged" to get
robust capture).
Actually, based on the idea in the link of my post, i already built a clock divider with 4 phases non-overlapping but, input clock of 4GHz and output clock 1 GHz. Of course, as your comments, i traded off such a large spikes at the falling egde like the capture below. However, it is still fine and could be some improvements next phase , i just want to test the function first . However, i want to do it with 8 phases with only 4 GHz clock input, could y give any suggetion ?
1632900145087.png

--- Updated ---

8 non-overlapping signals created from 2 signals? I can't think of any reasonable way of doing it without some more regi

1632901607195.png

As I mentioned first in thread, i referred to this idea to do it, but this provides merely 4 phases with resulting freq is equal to input clock /4, that means in this case, DCD = 25%. So Is there any method that helps to lower DCD to 12.5 % with input clock similar : 4GHz. Of course we can increase the number of combinational gates or DFF, but when i employed 3 bits counter, the phases will be 8 non overlaping however as a result my clock now will be divided by 8 (4/8 = 500MHz) that is not desired (expected 1GHz)
 
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KlausST

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Hi,

please draw a timing diagram of what you want.
I´m confused by all information ... what you not want.

Klaus
 

Anomis

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Hi,

please draw a timing diagram of what you want.
I´m confused by all information ... what you not want.

Klaus
sorry for missing your above comment,
generally, i hope it should be like this (sorry for my bad sketching skill)

1632903918160.png

fortunately, i find here an idea at last post(https://www.edaboard.com/threads/4-phases-non-overlapping-clock-generator.342504/) - of providing 4-non overlapping phases with only a half of intput clock. But im not sure about D complementary (DB) in such circuit for what purpose since in D-FF DB behaves like a output (inverter of D), getting Q1B (output) to another output (DB) does not make any sense

1.png
 
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KlausST

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generally, i hope it should be like this (sorry for my bad sketching skill)
The drawing is O.K.

Obviously you can´t use one clock edge on all FFs.
So either use rising edge and falling edge

Or use the AND gates of post#6...
(I guess a 1-of-8 decoder also uses logic gates)

Klaus
 

Anomis

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t The drawing is O.K.

Obviously you can´t use one clock edge on all FFs.
So either use rising edge and falling edge

Or use the AND gates of post#6...
(I guess a 1-of-8 decoder also uses logic gates)

Klaus
what do you mean by D0 D1, it should be Q0 &Q1 right?
 

D.A.(Tony)Stewart

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Not a solution, but this 12 phase 1 GHz DLL might offer some insight.

I know from experience that the prop delay of an XOR gate has skew or unequal delays due to differences in the internal path delays for each edge for CMOS when used as edge detectors. Read it backwards from the conclusion.
 

Anomis

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what do you mean by D0 D1, it should be Q0 &Q1 right?
thanks for your hint above, the circuit seems to be functioned but the "shape" is not that good because of high frequency operation and there are some unexpected shooting right after LO1 LO3 & LO7 in 1 period. Is there any ways to improve this issue, could y give me a suggestion ? honestly im famimilar with RF design rather than this mix-signal regrime but im getting familiar with kind of stuff these days
1632986196126.png

--- Updated ---

Not a solution, but this 12 phase 1 GHz DLL might offer some insight.

I know from experience that the prop delay of an XOR gate has skew or unequal delays due to differences in the internal path delays for each edge for CMOS when used as edge detectors. Read it backwards from the conclusion.
thanks for the document, i still keep reading it, but it seems to take days to digest the idea
 

KlausST

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Hi,

the "unexpected shooting" (is quite expectable with FPGA design) is also called "glitch" and happens due to signal runtime problems on combinatorial logic.
Internally they will happen. Externally they usually are avoided by using a D-FF at each output. But they need twice the input clock frequency. ... what again is a problem - I think

Klaus
 

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@KlausST, I don't think this is being done in an FPGA, I don't think there is a commercially available FPGA that is capable of this 1GHz operation or the 4GHz operation the OP has been discussing.

I suspect this was posted in the wrong section and should have been posted in the ASIC section. The waveforms shown are probably out of some simulation tool.

I would have moved it but by the time I saw it on Wednesday the post already had a bunch of replies, including by some moderators
 

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