qamesh
Newbie level 4
HI All.
I Have special board with a FMC connector that is supposed to provide a clock signal to my FPGA board (ZYNq Ultrascale+ board zCU102 ) through some specific pins on the FMC connector. The problem is, the Pins didicated for the clock from the Vendor are non-clock input pins on my board which casuese problems during synthesis. Does any one knows how can I get the external clock from non-clock input into the global clock net?.
I tried several ways, the last one was:
1. Get the input diff clock through an IBUFDS
2. Take the out put signal of the IBUFDS to BUFG
3. Connect the out put of the BUFG to MMCMs
4.use the command set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mopshub_emci_i/mopshub_top_emci_0/inst/sys_clk_emci0/clkin1_ibufds/O] in my constraints file. I dont know how critical is this command but it went well with vivado and I was able to generate the bitstream file of my design but I didnt see any clock signal later .
I Have special board with a FMC connector that is supposed to provide a clock signal to my FPGA board (ZYNq Ultrascale+ board zCU102 ) through some specific pins on the FMC connector. The problem is, the Pins didicated for the clock from the Vendor are non-clock input pins on my board which casuese problems during synthesis. Does any one knows how can I get the external clock from non-clock input into the global clock net?.
I tried several ways, the last one was:
1. Get the input diff clock through an IBUFDS
2. Take the out put signal of the IBUFDS to BUFG
3. Connect the out put of the BUFG to MMCMs
4.use the command set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mopshub_emci_i/mopshub_top_emci_0/inst/sys_clk_emci0/clkin1_ibufds/O] in my constraints file. I dont know how critical is this command but it went well with vivado and I was able to generate the bitstream file of my design but I didnt see any clock signal later .