Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Getting a clock signal from a non -CC PIN

Not open for further replies.


Newbie level 4
Nov 12, 2021
Reaction score
Trophy points
Activity points
HI All.
I Have special board with a FMC connector that is supposed to provide a clock signal to my FPGA board (ZYNq Ultrascale+ board zCU102 ) through some specific pins on the FMC connector. The problem is, the Pins didicated for the clock from the Vendor are non-clock input pins on my board which casuese problems during synthesis. Does any one knows how can I get the external clock from non-clock input into the global clock net?.
I tried several ways, the last one was:
1. Get the input diff clock through an IBUFDS
2. Take the out put signal of the IBUFDS to BUFG
3. Connect the out put of the BUFG to MMCMs
4.use the command set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mopshub_emci_i/mopshub_top_emci_0/inst/sys_clk_emci0/clkin1_ibufds/O] in my constraints file. I dont know how critical is this command but it went well with vivado and I was able to generate the bitstream file of my design but I didnt see any clock signal later .

I always use the 4th option to bring -in/get-out clock on a non-clock-capable pin!
It is easy to use this on your xdc.

Without the need to define any BUFG before?, and did you get a clean clock signal after?
A BUFG is needed when you need this clock to reach all parts of the FPGA. In that case a BUFG needs to be manually instantiated.
But if that clock is needed only for one region (use BUFR) or immediate surrounding regions (use BUFMR) then a BUFG is not needed.

For e.g. consider an RGMII i/f and the rgmii_rx_clk is being received through a non clock capable pin. The rgmii_rx_clk is needed only up to the Eth MAC PHY i/f and not after that. In such a case using BUFG to route the rgmii_rx_clk would be a waste.

btw - my answer is based on Xilinx 7 series FPGA clocking architecture!

Not open for further replies.

Part and Inventory Search

Welcome to