[SOLVED] Urgent! [frequency divider]

[jianhuachews]

Hi can anyone provide me vhdl codes for divide by 50 frequency divider circuit using flip-flops?
Thanks in adv.

 

[sv1437]

Did you google for the code? You can find the code for frequency divider online.

 

[vipinlal]

Here is the code:
VHDL coding tips and tricks: Clock Frequency converter in VHDL

 

[permute]

@jimmy_tag, I'm not sure you've seen both of the linked websites. the code between the two is different. For example, try both versions with the divide value set to 2. They don't behave the same, with your version outputting 110110110110, and the other generating 101010101010.

Your version might infer extra logic as you use less-than comparisons, instead of comparing =. both versions use 1 additional bit in the addition, with Vipin's potentially inferring a 32b addition in all cases.

  if (cnt = 1) then
    cnt <= HALF_TC;
    out_sig <= not out_sig;
  else
    cnt <= cnt - 1;
  end if;

The above structure works for the fixed division case. Only comparisons to a constant are used. only N/2 needs to be stored in cnt. The above will also work for the variable division case, but only changes clock rates at an edge. (thus a change to a very high value cannot be undone quickly). There are dozens of other ways to implement this.

 

[jianhuachews]

hey guys could anyone tell me what's the difference between use ieee.std_logic_arith.all; and use ieee.numeric_std.all; ?

Also... What does it mean when "if (counter < divide/2-1) then" continue from code.. I don't understand why i should do this for a divide by 50 freq divider..

if( rising_edge(Clk) ) then
	  if(counter < divide/2-1) then
		counter <= counter + 1;
		output_clk <= '0';
	elsif(counter < divide-1) then
		counter <= counter + 1;
		output_clk <= '1';
	else
		output_clk <= '0';
		counter <= 0;

 

[jianhuachews]

program

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity lab3C is port(   
	Clk, nreset: in std_logic;
	output_clk : out std_logic;
	divide_value : in integer
);

end ;

architecture Behavior of lab3C is

signal counter,divide : integer := 0;

begin

divide <= divide_value;

process(Clk,nreset)
begin
	if (nreset = '0') then
            output_clk <= '1';
            counter <= 0;
	elsif( rising_edge(Clk) ) then
	  if(counter < divide/2-1) then
		counter <= counter + 1;
		output_clk <= '0';
	elsif(counter < divide-1) then
		counter <= counter + 1;
		output_clk <= '1';
	else
		output_clk <= '0';
		counter <= 0;
	  end if;
	end if;
	
end process;   

end ;

TB

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity lab3cTB is
end;

architecture behavior of lab3cTB is
signal clk,output_clk,nreset : std_logic;
signal divide_value : integer;
constant clk_period : time := 10 ns;

begin
  -- Component Instantiation
uut: entity work.lab3C PORT MAP(
		clk => clk,
		output_clk => output_clk,
		nreset => nreset,
		divide_value => divide_value );

simulate : process
begin
	divide_value <= 50;
	wait for 500 ns;
	wait;
end process;

clk_process : process  --generates a 100 MHz clock.
begin
	nreset <= '0';
	wait for clk_period;
	nreset <= '1';
	wait for clk_period;
	clk <= '0';
	wait for clk_period/2;  --for 5 ns signal is '0'.
	clk <= '1';
	wait for clk_period/2;  --for next 5 ns signal is '1'.
end process;

end;

Hi guys i added in nreset to make it so that when nreset is 0, the count would be reset and the output_clk will not be affected but it seems like i screw it up can anyone help with it?

 

[sanju_]

hi
difference between use ieee.std_logic_arith.all; and use ieee.numeric_std.all;
sol:we never use "ieee.std_logic_arith.all" library for
synthesizable component.
always use ieee.numeric_std.all.

What does it mean when "if (counter < divide/2-1) then" continue from code.

sol:when you want 50 frequency divider circuit
you are calculating from zero so 0 to 24((counter < divide/2-1) ==(counter < (50/2)-1)==(counter < 24) ) changing clk to negative to positive or vice versa
half cycle remaining another half cycle..

 

[jianhuachews]

Oh.. I initially thought tht a "divide by 50 frequency divider" means to have 50 in_clk waveforms to generate a 1 out_clk waveforms. I totally have no idea wht i was doing.. Thanks so much anyways

 

[sanju_]

hi
"I initially thought tht a "divide by 50 frequency divider" means to have 50 in_clk waveforms to generate a 1 out_clk waveforms"-->is correct
but in that 25 cycle or waveforms take positive level and remaining 25 will take negative level
so in that line in your code its counting starts from zero so ending at 24 (counter < divide/2-1) think this is positive level and another condition
(counter < divide-1) is 49 (25 to 49 another 25 cycles)think it is negative level.....so its counts 0 to 49 == 50...
this is just frequency divider not the code explaination you mentioned above...

 

[jianhuachews]

oh.... ok i think i roughly had an idea on what's going on now thanks for helping out sanju! :grin:

 

[jianhuachews]

Hi guys.

Right now i working on to design a circuit to obtain a 2hz frequency from a 50Mhz clk_in which actually means im doing a obvious divide by 25 million freq divider circuit. But the thing is i was told that i should not use integer* in my program code and instead, i should use the actual divide value needed. I was advised to use a constant or generic in my program. I forgot the real purpose behind it and all i remembered was something that goes like that "there is no input drive in the real board that allows you to set the divide value, the division should be an internal thing within the program."



*Interger

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity lab3d is port(   
	Clk: in std_logic;
	output_clk : out std_logic;
	divide_value : in integer
);

end ;

architecture Behavior of lab3d is
[B][COLOR="#FF0000"]
signal counter,divide : integer := 0;[/COLOR][/B]

begin

divide <= divide_value;

process(Clk)
begin
	if( rising_edge(Clk) ) then
	  if(counter < divide/2-1) then
		counter <= counter + 1;
		output_clk <= '0';
	  elsif(counter < divide-1) then
		counter <= counter + 1;
		output_clk <= '1';
	else 
		counter <= 0;
		output_clk <= '0';
	  end if;
	end if;
end process;   

end ;

I don't understand what's with integer or constant. Also i've searched online guides and they have codes like

 generic (DivideValue : integer := 25000000);

So what is the difference if between the 2 sets of "integer" and "generic(something: integer)" ? It feels the same to me, am i right?

 

[preet]

Dear jianhuachews

The purpose of declaring it as generic or constant, is to make component general purpose, so that you can use it in future for any other frequency value

Regards

Preet

 

[sanju_]

hi again
"generic (something : type := constant);"
its an syntax for generic it is used to represent global constant in that program..


general syntax

entity entity-name i s
generic (
generic-name : data-type : = default-values ;
generic-name : data-type : = default-values ;
generic-name : data-type : = default-values
)
p o r t (
port-name : mode data-type ;
) ;
end entity-name;

 

[jianhuachews]

Global meaning i can define as many constant as needed right? Ok so that's for generic, thanks!!

I tried another way of programming it here goes..

library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.all;

 entity sec_clk is
    Port (
           Clk             : in  std_logic;
           op       : out std_logic
    );
 end sec_clk;

 architecture RTC of sec_clk is
[COLOR="#FF0000"]   constant max_count : natural := 25000000;[/COLOR]
  
 begin
      
    compteur : process(Clk)
       [COLOR="#FFA07A"] variable count : natural range 0 to max_count;[/COLOR]
    begin
	if rising_edge(Clk) then
            if count < max_count/2 then
                op    <='1';
                count := count + 1;
            elsif count < max_count then
                op    <='0';
                count := count + 1;
            else
                count := 0;
                op    <='1';
            end if;
        end if;
    end process compteur;
 end RTC;

I modified the program from a reference source but i don't understand what does the constant max_count : natural := 25000000; stands for..

This sentence too i dn't understand! variable count : natural range 0 to max_count;

Also, am i right to put constant max_count : natural := 25000000; if i want a 2hz o/p from a 50Mhz i/p?

 

[sanju_]

hi
"but i don't understand what does the constant max_count : natural := 25000000; stands for.."
you need 2hz from 50mhz so it will become 1hz from 25mhz....
max_count : natural := 25000000;(this line of your code defines for 1hz from 25000000 if it will repeat again it will becomes 2hz from 50000000)

 

[jianhuachews]

max_count : natural := 25000000;(this line of your code defines for 1hz from 25000000 if it will repeat again it will becomes 2hz from 50000000)

Oh!!!!! So in simple words it actually means max_count is the frequency input! Ok cool i got it but what does "natural" means?

 

[sanju_]

hi
NATURAL: non-negative integers(from 0 to +2,147,483,647)


download this text books for syntax problems and starting vhdl code
FPGA Prototyping by VHDL Examples
and
Circuit design with VHDL by Volnei . Pedroni
search in google i cant post links

 

[vipinlal]

Some copied content after googling(definitions of integer,natural and positive data types):

type INTEGER is range -2147483648 to 2147483647;
subtype Natural is Integer range 0 to 2147483647;
subtype Positive is Integer range 1 to 2147483647;

Do a quick googling if you have a doubt. Ask in the forum when it doesnt help.

 

[jianhuachews]

hi again sanju and vipinlal, i got it now thanks for looking up for me from search engine! :wink: