[SOLVED] Universal Shift Register

[zekkragnos]

Hi I'm new to VHDL and I have to create a universal shift Register. I have to use a D type flip flop, a 4 to 1 multiplexer and a tri-state buffer to complete it. The register specifications are: parallel load capability, shift left, shift right, stores or hold data, must be synchronous to the clock edge and outputs should be tristate able.
I have created the 4 to 1 Mux, the D typer Flip Flop, the Tri-State Buffer and now I'm trying to connect it all as an FSM. I still haven't accomplished all the desired specifications and would love to have any help.

 

[imbichie]

In the Mux code i think the Sel is Sel : in STD_LOGIC_VECTOR(1 downto 0) instead of Sel : in STD_LOGIC_VECTOR(2 downto 0).

In the DFF code you need to specify whether the D-flip flop is positive edge triggered or negetive edge triggered, so use process (rising_edge(CLK)) for positive or process (falling_edge(CLK)) for negative instead of process(CLK).

Just check this and try again.

 

[zekkragnos]

In the Mux code i think the Sel is Sel : in STD_LOGIC_VECTOR(1 downto 0) instead of Sel : in STD_LOGIC_VECTOR(2 downto 0).

In the DFF code you need to specify whether the D-flip flop is positive edge triggered or negetive edge triggered, so use process (rising_edge(CLK)) for positive or process (falling_edge(CLK)) for negative instead of process(CLK).

Just check this and try again.

Ok I did that but also in the register, are the connections connected properly? I feel like the Mux and and DFF are but the TSB is not properly connected since all the outputs have to be tristate able

 

[imbichie]

Here the TSB input TSB_IN is connected to the output Qn of DFF and the TSB input TSB_EN is connected to the Q of DFF.
So when the value of Q is 1, then TSB_EN became 1, and the Qn must be 0, so TSB_IN became 0 and the output of the TSB_OUT bacame 0
also when the Q is 0, then the TSB_EN bacame 0, and the Qn must be 1, so TSB_IN became 1 and the output of the TSB_OUT bacame Z.
So under these connection the value of TSB_OUT can be either 1 or 0, let me know if i am mistaken.

 

[ads-ee]

In the DFF code you need to specify whether the D-flip flop is positive edge triggered or negetive edge triggered, so use process (rising_edge(CLK)) for positive or process (falling_edge(CLK)) for negative instead of process(CLK).

This is incorrect.

process (CLK) is correct

if rising_edge(CLK) then is what is needed for a rising edge D flip-flop.

You should really use named association to improve readability of the instantiated modules and ensure that port changes won't result in misconnected ports.

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Code VHDL - [expand]
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U1:Mux PORT MAP (
    in0 => il,
    in1 => Qt(2),
    in2 => i(3),
    in3 => Qt(3),
    Sel => Sel,
    Mux_Out => Mux_Out(3));

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and now I'm trying to connect it all as an FSM.

Why do you need an FSM? I didn't see anything obviously wrong with the top level connections of the DFF, MUX, and TSB. All that is required to use the register is the shift left input, shift right input, the load input, the shift register outputs, the clock, and the mode select, which you have as the ports on General_Purpose_Register.

I've got a question about this task. Was separating the design into a D flip-flop, tri-state buffer, and mux a requirement of the design? I'm assuming this is a school assignment (still don't understand the idea behind teaching students to designing this way).

- - - Updated - - -

Here the TSB input TSB_IN is connected to the output Qn of DFF and the TSB input TSB_EN is connected to the Q of DFF.
So when the value of Q is 1, then TSB_EN became 1, and the Qn must be 0, so TSB_IN became 0 and the output of the TSB_OUT bacame 0
also when the Q is 0, then the TSB_EN bacame 0, and the Qn must be 1, so TSB_IN became 1 and the output of the TSB_OUT bacame Z.
So under these connection the value of TSB_OUT can be either 1 or 0, let me know if i am mistaken.

So you're making a pseudo open collector output not a tri-state output. Unless that was part of your "requirements" what you coded for the TSB isn't a tri-state output. You would have to add an input to General_Purpose_Register to enable the outputs like oe : in std_logic; and use that to enable ('1') and tri-state ('0') the TSB_OUT port.

 

[imbichie]

This is incorrect.

process (CLK) is correct

if rising_edge(CLK) then is what is needed for a rising edge D flip-flop.

Hi ads-ee,

Yes, I am mistaked, actually my intention was if (rising_edge(clk)) or if (falling_edge(clk)),
but by mistake i put process.

 

[zekkragnos]

Sorry it doesn't need an FSM, I've been working with FSM a lot so I accidently wrote that. I changed the connections to your suggestions like this: