PLL dynamic phase shift approach

[promach]

As for PLL dynamic phase shift approach, I have few questions:

1. Could I actually generate a 90 degree phase-shifted clock from CLK_OUT2 using DCM_SP Settings ?
Could I actually generate a 270 degree phase shifted clock from CLK_OUT4 using DCM_SP Settings ?

2. What about PLL_BASE Settings which seems to have the phase shift capability as well ?

 

[promach]

When I simulate my design with DCM, I have Warning : Input Clock Period Jitter on instance test_ddr3_memory_controller.ddr3_control.pll_ddr.dcm_sp_inst exceeds 1.000 ns. Locked CLKIN Period = 0.822. Current CLKIN Period = 0.822. ?

Why PLL DCM could not be locked ?

 

[promach]

I have solved the locked issue above


For PLL dynamic phase shift, ck_dynamic output is incorrect with respect to udqs_r

Note: I try to read the Xilinx support webpage on dynamic phase shift FAQ, but I still could not find what I want in order to debug the non-working dynamic phase shift.

http://www.xilinx.com/support/answers/52806.html

http://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L684-L704