Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PLL dynamic phase shift approach

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,158
Helped
2
Reputation
4
Reaction score
4
Trophy points
38
Activity points
10,117
As for PLL dynamic phase shift approach, I have few questions:

1. Could I actually generate a 90 degree phase-shifted clock from CLK_OUT2 using DCM_SP Settings ?
Could I actually generate a 270 degree phase shifted clock from CLK_OUT4 using DCM_SP Settings ?

2. What about PLL_BASE Settings which seems to have the phase shift capability as well ?

1627476545468.png

1627476552803.png

1627476562951.png
 

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,158
Helped
2
Reputation
4
Reaction score
4
Trophy points
38
Activity points
10,117
When I simulate my design with DCM, I have Warning : Input Clock Period Jitter on instance test_ddr3_memory_controller.ddr3_control.pll_ddr.dcm_sp_inst exceeds 1.000 ns. Locked CLKIN Period = 0.822. Current CLKIN Period = 0.822. ?

Why PLL DCM could not be locked ?

1627618527841.png
 

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,158
Helped
2
Reputation
4
Reaction score
4
Trophy points
38
Activity points
10,117

Attachments

  • DDR_Xilinx_ISE.zip
    5.5 MB · Views: 0

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top