Understanding DDR size from DDR datasheet

[hioyo]

Below image is from micron DDR datasheet.

May I know what here what are 32Meg and x4 represents here.

 

[barry]

4 banks of 32 Meg x 4 bits

It's like any other memory, address space x data width. The only difference here is there are 4 banks.

 

[hioyo]

What exactly mean by bank,is it same as page

 

[FvM]

bank,is it same as page

No. You find the answer in the datasheet if you continue reading after the title page.

The banks of a DDR memory can partly operate in parallel. E.g. one bank is outputting data while the other is preparing the next read.

 

[hioyo]

Thank you.May I know how to calculate total size if the information is given like this 32 Meg x 4 x 8 Banks

 

[KlausST]

Hi,

What exactly are you asking for? What "size information" are you after?

Datasheet as well as post#2 is rather exact and clear.

Klaus

 

[hioyo]

The datasheet tells it's size. My question is if they give something like this 32 Meg x 4 x 8 Banks.
How to arrive that size value which is mentioned in the datasheet

 

[KlausST]

Hi,

I don't understand "how to arrive".
32 Meg x 4 x 8 Banks is the size (and organisation information) of the memory inside the accirding chip.

Compare it with a chess filed.
It is organized in 8 x 8 fields.
It means it has 8 rows, 8 columns and thus 8 x 8 = 64 single fields

Klaus

 

[hioyo]

32X4X4 = 512Megabits
512*.125MB = 64MB

 

[KlausST]

Hi,

is this a solution or a question?

you wrote 64MB. So 64MBytes?
I don´t recommend to say so. Because the data width is no "full byte". Your data width is just 4 bits.
So you need two chips to get a full byte (seen from data width)

Use the other chip: 16M x 8 x 4 banks to get true 64MBytes

or the 8M x 16 x 4 banks to get 8MWords

Klaus

 

[hioyo]

I just tried to calculate the size of memory with below spec

32X4X4 = 512Megabits
512*.125MB = 64MB

Yes it is 64MB

 

[FvM]

512 Mb (Megabit) is already written in the first datasheet line. If you have any doubts what this means, you would read the "General Description" paragraph following on the next pages.

 

[hioyo]

Yes it is written there.But I don't know how they arrived that value.
Now I think it is clear for me.

 

[engr_joni_ee]

Hi, can someone please summarize the address width and data lines width for this memory 512 M bits or 64 M bytes to be connected to FPGA ?

For 64 Mega memory locations, we actually need 26 bit address lines if there is no multiplexing between addressing.

In case of multiplexing, can someone please explain how the memory is organized physically and how to access 64 Mega bytes memory location