kornev.online
Newbie
HI!
I am tracing my first DDR2 PCB with Cyclone V and I can't find exact information about CLK vs DSQ vs ADR lenght matching.
External Memory Interface Handbook Volume 2: Design Guidelines from Intel says that:"All data, address, and command signals must have matched length traces ±50 ps.", but about Clock: "equal to the signals in the Address/Command Group or up to 100 mils (2.54 mm) longer than the signals in theAddress/Command Group."
AMD support forum says:"The maximum electrical delay between any DQS/DQS # and CK/CK # must be < ±25 ps."
Microchip says:"Match DQS to clock loosely Yes" for DDR2.
But when I am looking at real designs Address and Clock lines used to be longer than DQS.
At Altera Cyclone IV GX FPGA Development Kit:
Data lines are 28-40mm, Clock 47mm, Address lines are 46-58mm.
At SO-DIMM module reference layout from JEDEC:
Data lines are about 17mm, Clock is 27mm, Address lines are about 56 mm.
All byte lanes matches with their DQS.
All DQS matches between each other.
But what about CLK vs DSQ vs ADR?
I am tracing my first DDR2 PCB with Cyclone V and I can't find exact information about CLK vs DSQ vs ADR lenght matching.
External Memory Interface Handbook Volume 2: Design Guidelines from Intel says that:"All data, address, and command signals must have matched length traces ±50 ps.", but about Clock: "equal to the signals in the Address/Command Group or up to 100 mils (2.54 mm) longer than the signals in theAddress/Command Group."
AMD support forum says:"The maximum electrical delay between any DQS/DQS # and CK/CK # must be < ±25 ps."
Microchip says:"Match DQS to clock loosely Yes" for DDR2.
But when I am looking at real designs Address and Clock lines used to be longer than DQS.
At Altera Cyclone IV GX FPGA Development Kit:
Data lines are 28-40mm, Clock 47mm, Address lines are 46-58mm.
At SO-DIMM module reference layout from JEDEC:
Data lines are about 17mm, Clock is 27mm, Address lines are about 56 mm.
All byte lanes matches with their DQS.
All DQS matches between each other.
But what about CLK vs DSQ vs ADR?
