robertzhan
Newbie level 4
altera_io_begin what is
Just as title, I have to detect two rising edge and write the routine as follows. When it was compiled, there is error:
Error: VHDL error at soft_switching.vhd(69): can't infer register for signal "counter[0]" because signal does not hold its value outside clock edge
I don't why and hope kind person can help me
Robert Zhan
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
-- Entity Declaration
ENTITY soft_switching IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
pwm : IN STD_LOGIC;
ilt : IN STD_LOGIC;
clk : IN STD_LOGIC;
pwm_delay : OUT STD_LOGIC;
tab : OUT STD_LOGIC := '0';
tl : OUT STD_LOGIC := '1'
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END soft_switching;
-- Architecture Body
ARCHITECTURE soft_switching_architecture OF soft_switching IS
SIGNAL counter : integer := 0;
SIGNAL flag : bit;
SIGNAL pwm_temp : STD_LOGIC;
BEGIN
p01: process(clk, ilt, pwm) is
begin
IF (clk'event AND clk = '1') THEN
counter <= counter + 1;
IF (ilt'event AND ilt = '1') THEN
tl <= '0';
IF (counter >=40 AND counter <100) THEN
pwm_delay <= pwm;
ELSIF (counter >= 100) THEN
tab <= '0';
pwm_delay <= '0';
counter <= 0;
END IF;
END IF;
END IF;
end process p01;
Just as title, I have to detect two rising edge and write the routine as follows. When it was compiled, there is error:
Error: VHDL error at soft_switching.vhd(69): can't infer register for signal "counter[0]" because signal does not hold its value outside clock edge
I don't why and hope kind person can help me
Robert Zhan
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
-- Entity Declaration
ENTITY soft_switching IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
pwm : IN STD_LOGIC;
ilt : IN STD_LOGIC;
clk : IN STD_LOGIC;
pwm_delay : OUT STD_LOGIC;
tab : OUT STD_LOGIC := '0';
tl : OUT STD_LOGIC := '1'
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END soft_switching;
-- Architecture Body
ARCHITECTURE soft_switching_architecture OF soft_switching IS
SIGNAL counter : integer := 0;
SIGNAL flag : bit;
SIGNAL pwm_temp : STD_LOGIC;
BEGIN
p01: process(clk, ilt, pwm) is
begin
IF (clk'event AND clk = '1') THEN
counter <= counter + 1;
IF (ilt'event AND ilt = '1') THEN
tl <= '0';
IF (counter >=40 AND counter <100) THEN
pwm_delay <= pwm;
ELSIF (counter >= 100) THEN
tab <= '0';
pwm_delay <= '0';
counter <= 0;
END IF;
END IF;
END IF;
end process p01;