Two rising edge in one process

[robertzhan]

altera_io_begin what is

Just as title, I have to detect two rising edge and write the routine as follows. When it was compiled, there is error:
Error: VHDL error at soft_switching.vhd(69): can't infer register for signal "counter[0]" because signal does not hold its value outside clock edge

I don't why and hope kind person can help me

Robert Zhan


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


-- Entity Declaration

ENTITY soft_switching IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
pwm : IN STD_LOGIC;
ilt : IN STD_LOGIC;
clk : IN STD_LOGIC;
pwm_delay : OUT STD_LOGIC;
tab : OUT STD_LOGIC := '0';
tl : OUT STD_LOGIC := '1'
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

END soft_switching;


-- Architecture Body

ARCHITECTURE soft_switching_architecture OF soft_switching IS

SIGNAL counter : integer := 0;
SIGNAL flag : bit;
SIGNAL pwm_temp : STD_LOGIC;

BEGIN

p01: process(clk, ilt, pwm) is
begin
IF (clk'event AND clk = '1') THEN
counter <= counter + 1;
IF (ilt'event AND ilt = '1') THEN
tl <= '0';
IF (counter >=40 AND counter <100) THEN
pwm_delay <= pwm;
ELSIF (counter >= 100) THEN
tab <= '0';
pwm_delay <= '0';
counter <= 0;

END IF;


END IF;
END IF;
end process p01;

 

[shawndaking]

vhdl code for detecting rising edge

This is awful VHDL Code.

What Is Your Target Exactly.

What each Input/Output Is Use For ?

 

[sp]

use 2 processes in ur vhdl code u might b able to detect both edges...

shawndaking please b gentle to new member(s)...

regards,
sp

 

[nand_gates]

Dear Robert Zhan,
Ur problem is you dont think about the hardware when you are writing VHDL code.
What I mean is this VHDL is a Hardware description Language. There has to be some
hardware first, then you VHDL to just describe it.
Now may question to you is can you draw digital logic circuit which you want to
describe in VHDL using above code??

Regards
nand_gates

 

[sp]

i have see this many times (i agree though..heheh)

 Ur problem is you dont think about the hardware when you are writing VHDL code.
What I mean is this VHDL is a Hardware description Language.

but as designing more more complex design or in behavioral description... design by drawing digital logic is quite impossible already(lazy perhaps)... this is the "abstraction level"

to avoid " for the tree, miss the forest"...

regards,
sp

 

[robertzhan]

Thank you for all ur kind suggestions.

I'll think about it more clearly and then to finish it.

Best regards

Robert Zhan