Nov 7, 2007 #1 V vlsi_freak Full Member level 2 Joined Sep 3, 2007 Messages 127 Helped 14 Reputation 28 Reaction score 8 Trophy points 1,298 Activity points 2,041 Hi. Is there any problem in using tristate 'Z' in FPGA's/ASIC's. Most of the people says that it is not a good practise to use tristate in FPGA's. Please share your ideas. Thanks
Hi. Is there any problem in using tristate 'Z' in FPGA's/ASIC's. Most of the people says that it is not a good practise to use tristate in FPGA's. Please share your ideas. Thanks
Nov 7, 2007 #2 F firewire2035 Member level 1 Joined Oct 10, 2004 Messages 35 Helped 2 Reputation 4 Reaction score 1 Trophy points 1,288 Activity points 192 #1 tristate buses cannot be structurally tested for ASIC, i.e. DFT. #2 high leakage current can break system power specification. #3 accidental bus contention can lower ASIC reliability/yield, etc.
#1 tristate buses cannot be structurally tested for ASIC, i.e. DFT. #2 high leakage current can break system power specification. #3 accidental bus contention can lower ASIC reliability/yield, etc.