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Tristate in FPGA/ASIC

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vlsi_freak

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Hi.

Is there any problem in using tristate 'Z' in FPGA's/ASIC's.

Most of the people says that it is not a good practise to use tristate in FPGA's.

Please share your ideas.

Thanks
 

firewire2035

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#1 tristate buses cannot be structurally tested for ASIC, i.e. DFT.

#2 high leakage current can break system power specification.

#3 accidental bus contention can lower ASIC reliability/yield, etc.
 

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