Tristate in FPGA/ASIC

[vlsi_freak]

Hi.

Is there any problem in using tristate 'Z' in FPGA's/ASIC's.

Most of the people says that it is not a good practise to use tristate in FPGA's.

Please share your ideas.

Thanks

 

[firewire2035]

#1 tristate buses cannot be structurally tested for ASIC, i.e. DFT.

#2 high leakage current can break system power specification.

#3 accidental bus contention can lower ASIC reliability/yield, etc.