Hello everybody,
I want to connect the IO cells(pads) to the final schematic design. These cells according to the manual can be used for IO voltages of 1.8, 2.5 and 3.3V. Is there some way to make the design tool ( Cadence Virtuoso ) understand what voltage am i going to use? There are some global sources available at the IO cell library ( i.e TAVDD18, TAVDD25 , TAVDD33) but i havent figured out how to use them.
Again according to the manual, the ESD protection is embedded in these cells. So , i connect correctly the appropriate Power Clamp cell between the power and ground cells and test the clamping.
The stimulus is generated through a charged capacitor in series with a resistance , that discharges to an input pad. When i run a transient simulation, i should see the voltage of the input pad clamp the discharge to around 0V rather quickly ( a couple of us ) but it seems that it takes around 200ms (!). If i run it for only some us, i get a "steady" state at about 9V ( that will surely destroy the device ).
Any advice?
Hello,
I am trying to simulate HBM , and as far as i know during such an ESD event the power rail is floating (? ). The approach we will use will be Area-I/o flipchip so there will not be any pad ring.
Also the technology is TSMC 65nm
Thank you for your answer
If you are using Area IO, then ESD protection is up to you to design. The IO library manual still is the first place to start as they have recommendations and possibly a stand alone ESD cell that has to be used (not in ring fashion).
But according to the manual ESD protection is embedded in power/ground/IO cells, so why would ESD protection be up to me to design? I will just pop these cells around?
Unfortunatelly the IO library manual is pretty confusing.
A portion of the ESD protection sits on the cell itself, of course. But the ESD protection scheme is only complete when the cells are abutted to form a rail. If using area IO, you don't have a rail. But you are still in charge of providing ESD protection beyond what the cell delivers.
TSMC manuals are known for being garbage. Good luck.
Well i understand , thank you! If the cell now has, lets say, double diode embedded would I need to add an appropriate size GGNMOS for instance? Or another pair of double diodes?
Maybe something is missing with the trigger part?
And yes for HBM analysis, the power rails have to be floating, but your netlist should have a 0 (ground) node in order to SPICE work successfully, and your circuit and the charge generator should be connected to same ground node.
Thank you for you answer . I do have a ground (otherwise the simulator wont work indeed ) but i dont have a circuit . The input pad ( that should connect to a terminal of a device lets say ) is left floating and i am measuring the voltage at that node. It shouldnt make a difference if I left it floating or connect it to a device ( the simplest circuit ) right?
I don't understand your point, what do you mean by "i don't have a circuit" ? I assumed you have your PAD design that you are instantiated in a ESD HBM testbench in order to simulate the response.
I assume your "PAD" cell is your I/O block and you are just simulating ESD response of your I/O block, by discharging an ESD charge through the input/output pad (physical pad signal communicating with the external world). As far as I understood from your very first message, in your netlist you do also have power/ground cells, not just independent voltage sources. If this is the case, does your power/gnd cells have a lot of decoupling capacitors (and probably their own ESD circuitries) ? I think you are looking for reaching the "0V level" after the ESD is triggered. I remember simulating once upon in a time relatively "slow" discharging times to 0V when I use real power/ground cells in the netlist instead of just independent voltage sources, due to huge capacitance that has to charged/discharged. However, the pad voltage should go down below the allowed range much more quickly (few us). If the voltage level is in the allowed range within a short time, you can assume your circuit is protected.
I will contact them, thank you.
BTW what do you mean by " should not attack the gate of a MOS "? If the input pad is connected to the gate of a MOS, the overvoltage should be seen at that terminal right?
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