to meet timing without chainging RTLs

[ASIC_int]

What is the different technique to meet timing when timing fails without chaing the RTLs?

 

[AdvaRes]

simplify your design or parallelize/pipeline

 

[permute]

those are both changes to RTL.

I think he means more along the lines of changing RTL optimizations or synthesis settings.

 

[kalyanasv]

FPGA: Have fun with floor planning, can provide you some extra slack.

ASIC:i) change technology from LP to HP, ii) planning iii) routing wires ............................

Have fun

 

[ASIC_int]

The question which was asked to me probably wants along the lines of changing RTL optimizations or synthesis settings?

 

[dcreddy1980]

Here are some tips which might help in improving the timing :
1. Flattening of the design
2. Register Duplication
3. FSM state encoding (Can be changed in Xilinx Synthesis tool)
4. Register Balancing

 

[kbulusu]

IMHO, unless you analyze the timing path , you cant say what technique will help you meet the timing..so send your timing path and we can figure out why it failed and how we can meet the slack...