deepu_s_s
Full Member level 5
hi !
supppose the clocked synchronous state machine with the structure below is designed using D larches with active high C inputs as storage elements. For proper next-state operation,what relationships must be satisfied among the following timing parameteres?
tFmin,tFmax ----Min and Max propagation delay of the next state logic
tCQmin, tCQmax----Min and Max clock-to-output delay of a D latch
tDQmin,tDQmax----Min and Max data-to-output delay of a D latch
tsetup, thold---setup and hold times
tH,tL---clock high and low times.
supppose the clocked synchronous state machine with the structure below is designed using D larches with active high C inputs as storage elements. For proper next-state operation,what relationships must be satisfied among the following timing parameteres?
tFmin,tFmax ----Min and Max propagation delay of the next state logic
tCQmin, tCQmax----Min and Max clock-to-output delay of a D latch
tDQmin,tDQmax----Min and Max data-to-output delay of a D latch
tsetup, thold---setup and hold times
tH,tL---clock high and low times.
