[SOLVED] Timing question. Please explain

[sam33r]

Please explain the following question. Apologies if posted in wrong forum.

Q) The minimum and maximum delays between each set of successive gates are marked as
#(min: typical: max) ns and are marked on the output node of the driving gate.
(Remember the timing equations are ≤ and ≥ constraints). You also need the
following:
· T_setup = #(1 : 1 : 2) ns.
· T_hold = #(1: 1 :2) ns.
· T_skew = #(1: 1 : 1) ns for the clock.
· T_clock-Q = #(2 : 3 : 5) ns.
· T_logic = #(1 : 2 : 3) ns for each and every logic gate from any input to any
output.

Consider the following code (implemented exactly as described):
reg A, B, C, D, E;
always@(posedge clock)
begin
A <= D ? B : E;
B <= (A | C) & D;
C <= (A ^ B) & D;
D <= (A ^ B);
E <= A | D;


If this design was converted to a latch based design and “cycle stealing” was enabled,
what would the clock period be (assuming a 50% duty cycle and rounded to the nearest
integer)?
A. 5 ns
B. 10 ns
C. 9 ns
D. 14 ns
E. None of the above are correct.

 

[lostinxlation]

I'd explain if you tell us which part you don't understand.

 

[sam33r]

Thank you for the reply. I know the concept of cycle stealing in latches. I designed the logic from the verilog code and calculated the delay in the maximum logic. But the answer is not matching. Please tell me the general way to tackle such king of problems which include minimum clock period, set-up time hold time calculations. Thank you.

 

[lostinxlation]

Post your attempt.

In general, since you can't borrow the time from 1 cycle ahead, you only need to look into the current half cycle and the next half cycle and calculate the max time for each 1 cycle segment.

 

[sam33r]

Ahh! I got it where i was going wrong. Thanks for the help though.