negative timing checks sdf 2.1
Those SDFA errors have nothing to do with the simulator that you are using, it's all about the verilog library you used to run gate simulation. SDFA is just a PLI call to read the SDF file and modify the value in the verilog mode "specify" blocks. Synopsys has no idea how your verilog library models the cells, so it writes all the pathes out. If the path is not in your cell model, you will have a SDFA error. The simplest soluation is ignore those errors, all hack the verilog library file, add the required path, that's kind of hard.