Timing Calculator for Artisan .18um

[wicho]

tsmc_neg.v

I designed using TSMC .18um technology.

The library is Artisan SAGE-X standard cell.

To do pre-simulation befor layout, I generated sdf file from synopsys.
However during sdf annotation, i met annotation error.

The sdf file from synopsys is not good.

Who has timing calculator which TSMC design center makes?

Please give me advice...

 

[zyphor]

verilog timing 18um

SDF file format is standard base file, so you should check the error's root
cause . This is nothing to do with the timing caculator.

 

[yankuangtu]

tsmc_neg

you can check the version of SDF file that you write out and the version of the tools can check in!

 

[wicho]

sdfa error: could not find path

The followings are some error messages and relevant sdf.

L386888: SDFA Error: Could not find path S0 to Y in instance top.xtop.U57
L386889: SDFA Error: Could not find path S0 to Y in instance top.xtop.U57

(CELL
(CELLTYPE "MX2XL")
(INSTANCE U57)
(DELAY
(ABSOLUTE
(IOPATH A Y (0.206:0.334:0.334) (0.145:0.274:0.274))
(IOPATH B Y (0.193:0.313:0.313) (0.152:0.290:0.290))
(COND A == 1'b1 && B == 1'b0 (IOPATH S0 Y (0.164:0.265:0.265) (0.153:0.248:0.248)))
(COND A == 1'b0 && B == 1'b1 (IOPATH S0 Y (0.112:0.182:0.182) (0.139:0.226:0.226)))
(IOPATH (posedge S0) Y (0.179:0.290:0.290) (0.156:0.253:0.253))
(IOPATH (negedge S0) Y (0.164:0.265:0.265) (0.144:0.233:0.233))
)
)
)

L387520: SDFA Warning: Negative timing check limit -0.800000 set to 0

(CELL
(CELLTYPE "DFFSX1")
(INSTANCE reg_top/xreg_19C_reg0)
(DELAY
(ABSOLUTE
(IOPATH (posedge CK) Q (0.365:0.591:0.591) (0.318:0.515:0.515))
(IOPATH (negedge SN) Q (0.192:0.312:0.312) ())
(IOPATH (posedge CK) QN (0.219:0.355:0.355) (0.259:0.419:0.419))
(IOPATH (negedge SN) QN () (0.086:0.139:0.139))
)
)
(TIMINGCHECK
(WIDTH (posedge CK) (0.390:0.390:0.390))
(WIDTH (negedge CK) (0.640:0.640:0.640))
(SETUP (posedge D) (posedge CK) (0.066:0.107:0.107))
(SETUP (negedge D) (posedge CK) (0.151:0.247:0.247))
(HOLD (posedge D) (posedge CK) (-0.047:-0.076:-0.076))
(HOLD (negedge D) (posedge CK) (-0.060:-0.099:-0.099))
(RECOVERY (posedge SN) (posedge CK) (-0.002:-0.003:-0.003))
(WIDTH (negedge SN) (0.850:0.850:0.850))
)
)


The command to make sdf is "write_sdf -version 2.1 -context verilog".
So it is not version mismatch...

I didn't see COND sentence and negative number in other sdf which make timing calculator from samsung, faraday and epson etc...

Who can resolve this error?
Who can give me timing calculator for tsmc .18um?

 

[zyphor]

negative timing check limit

hopefuly, I think it is caused by the netlist & sdf mismatch.
You can check your netlist and find the path with error message.

 

[wicho]

sdfa warning: negative timing check limit

There is no mismatch between netlist and sdf.

When I using ModelSim, there is no annotation error.

This is error message from Verilog-XL.

Who has design kit from Global UniChip, PGC and Sota?

If anyone has it, please give me...

 

[Nobody]

hold timing in sdf + cond &&

You had better try latest verilog simulator .
Some of the edge sense description does not accept by old version verilog . Do you have tried the fixed script accompany with sage-x cell library ? It's another solution to solve your problem automaticly .

 

[wicho]

artisan calculation

Nobody, Thanks a lot...

The latest verilog-xl don't also accept edge sense description.

After using perl script, i didn't got sdf annotation error.

Anyway, who has tsmc 0.18um design kit?

 

[crystal]

sdf cell negative delay iopath

I've encountered the same problem like yours, wicho.

What I did was that I read in the Verilog netlist from DC into PrimeTime and then, from there, I write out the sdf file.

When I do back annotation with the sdf file from PrimeTime plus netlist from DC, the errors are gone. No problem at all.

It's just a mismatch problem within netlist & the sdf file on the ege sensitivity description.

 

[kfy]

sdf file format synopsys

Hi ,

(1)
(IOPATH (posedge S0) Y (0.179:0.290:0.290) (0.156:0.253:0.253))
(IOPATH (negedge S0) Y (0.164:0.265:0.265) (0.144:0.233:0.233))

This Error messge is indicated that the IO path are different between Synopsys and Verilog model.

You should check the IO path of (posedge S0=>Y) and (negedeg S0=>Y) whether them are in verilog model.


(2)
For negative setup/hold time, you should use negative verilog mode.
In artisan lib, you can find a file named tsmc_neg.v.
Then, you also need add +neg_tchk in verilog command line to enable negative timing check.

FYI

Kevin

 

[farmerwang]

negative timing checks sdf 2.1

Those SDFA errors have nothing to do with the simulator that you are using, it's all about the verilog library you used to run gate simulation. SDFA is just a PLI call to read the SDF file and modify the value in the verilog mode "specify" blocks. Synopsys has no idea how your verilog library models the cells, so it writes all the pathes out. If the path is not in your cell model, you will have a SDFA error. The simplest soluation is ignore those errors, all hack the verilog library file, add the required path, that's kind of hard.