Hi All,
I have some doubt regarding timing arc. What is timing arcs. Is there any hardcore rule that if any port is asynchronous signal then it should have timing arc??
Hi All,
I have some doubt regarding timing arc. What is timing arcs. Is there any hardcore rule that if any port is asynchronous signal then it should have timing arc??
the rule is simple: any input that causes a change to an output is considered during std cell characterization. the tools that are farther up in the implementation chain need to know the delay and power consumption associated with a toggle on the input.