propagate timing critical busy signal through several modules

[eda_student]

Hi,
I have several modules (lets say 6) in a pipeline fashion.
module1 <-> module2 <-> .... <-> modulen

The data flows from module1 to modulen direction whereas backpressure in terms of busy signal flows from modulen to module1 direction.

The way I encoded this busy signal in each module is: I take the input busy from later module(for e.g. module2) and AND with some internal signal to generate output busy in previous module(for e.g. module1).

In synthesis I have problem meeting timing by some 100 ps.

I would like to break this path to meet timing but still follow pipelining.

Is there any way to do that?

Some Ideas will be appreciated.

Thanks

--- Updated Oct 10, 2023 ---

I use verilog for the coding

 

[std_match]

Designing Skid Buffers for Pipelines – Chipmunk Logic

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[eda_student]

Designing Skid Buffers for Pipelines – Chipmunk Logic

5 min read: What are Skid Buffers? How is it useful while designing elastic pipelines? How to design a Skid Buffer in Verilog / VHDL? Read on...

chipmunklogic.com

Approach seems to be fine but spyglass complain about implementation: mixing synchronous and asynchronous part together.