Testing of IC CMOS Inverter

[mohazaga]

cmos inverter overshoot

Hi ,,,

I design a CMOS inverter using 0.35u process, and I test its output by input different frequency square pulses.
The output of the inverter get distorted after 1M, is that due to RC parasitic introduced by fab. process.
Also, why there is overshoot and undershoot ate beginning of rise/fall of output pulse? is that due of RCL parasitic of IC pad contact?

Could you help please?
See the output at input of 5k, 50k, 200k, 2M & 5M.

Freq-5KHz

Freq-50KHz

Freq-200KHz

Freq-2MHz

Freq-5MHz

 

[dalraist]

cmos inverter+overshoot

The output of the inverter get distorted after 1M, is that due to RC parasitic introduced by fab. process.

Yes, it is.

Also, why there is overshoot and undershoot ate beginning of rise/fall of output pulse? is that due of RCL parasitic of IC pad contact?

The overshoot and undershoot are mainly due to Cgd (capacitance between gate and drain) of the 2 transistors.
At high frequency, this capacitance propagates the input signal directly to the output node before the inverter can reach the stability.

 

[mohazaga]

inverter under shoot

Hi,

The overshoot/undershoot is due to Cgd or Cdb (Drain-Bulk) of PMOS and NMOS?
thanks

 

[dalraist]

parasitic rc cmos inverter

It is due to Cgd which at high frequency becomes a "short" from In and Out of the Inverter.

 

[mohazaga]

inverter overshoot miller effect

Hi ,,,

This overshoot/undershoot is due to the transmission of the input slew to the output throughout the input-to-output coupling capacitance (Auvergne, Daga et al. 2000). That coupling capacitance is affect of Cgd-p,n overlap capacitances at the output, and taking into account the so-called Miller effect (Rabaey, Chandrakasan et al. 2003).

Is that OK
Thanx