Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Problem with switched capacitor inverter (flying capacitor inverter)


Newbie level 4
May 12, 2024
Reaction score
Trophy points
Activity points
I am trying to design a charge pump inverter (also known as flying capacitor inverter) whi. The idea is simple; using Vdd charge a capacitor in clock phase 1. In clock phase 2, disconnect it from the VDD and simultaneously connect its +ve terminal to ground and -ve terminal to a storage capacitor in clock phase 2. This is shown in the image below:


I have recreated this in Cadence and trying to simulate it.

As can be seen in the left side two switches (upper PMOS and lower NMOS), charge cap to +8V in phase-1. In the phase-2, right side switches (both NMOS), upper one brings +ve terminal to GND, hence at the -ve terminal of the cap, we get develop -8V. This becomes a problem for NMOS switches connected at the lower terminal of the cap.

1st problem: The negative voltage at the cap causes these NMOS to turn on (as the source of NMOS is defined to be the lower potential) if the gate is at 0V
2nd problem: The body/bulk of these NMOS may become forward biased due to the presence of negative voltage at their S/D if not biased to an even lower or equal voltage that is -8V or less (-10V maybe)

Both these issues have been discussed in Texas Instruments LMC7660. I copy the relevant passage from page 6 below:

In the circuit of Figure 11, S1 is a P-channel device and S2, S3, and S4 are N-channel devices. Because the
output is biased below ground, it is important that the p− wells of S3 and S4 never become forward biased with
respect to either their sources or drains. A substrate logic circuit specifies that these p− wells are always held at
the proper voltage. Under all conditions S4 p− well must be at the lowest potential in the circuit. To switch off S4,
a level translator generates VGS4 = 0V, and this is accomplished by biasing the level translator from the S4 p−

They show in the datasheet how the LMC7660 is designed:


They bias the bulk of S3 and S4 with substrate logic to possibly another -ve voltage and use the level translator to control the gates of these switches.

Using this understanding I made another simulation which connects bulk of these switches to a control signal where is phase 1 we bias the lower NMOS switches to 0V and in phase 2 the bulk is tied to -10V. The gate voltages will be generated compared to which terminal has lowest potential.


Right now I am having difficulty with getting it to work. The problem is that the -10V at the bulk appears on the cf- node and on C41 storage capacitor which shouldn't be possible
In simulation this particular topology (flying capacitor) has lent itself to auto-biasing, where transistors derive their bias not from a clock signal but from the circuit itself. At each position I must test an N-device and a P-device, then see if the node above or below provides sufficient bias to turn it on and off at the needed time. Bias voltage might come from a supply rail.

I never know which combination will work. If no combination works then I have to resort to applying the original clock signal, or even create a new clock signal.

The initial H-bridge with flying capacitor can be duplicated to several stages. (Capacitors charge in parallel during one half of a cycle, then discharge in series to the load.) The key of course is to discover the proper combination of N-devices and P-devices (and sometimes diodes if you can accept .7 V drop) Since the purpose is to multiply voltages from stage to stage (H-bridges), it becomes a challenge to derive the proper bias within each stage. I find it's a study in itself. The benefit is that the same construction can be used in other topologies using transistors.
Indeed finding the correct combination and knowing which bias voltage to apply to turn ON and OFF is a challenge. For my application, I only require the inverted supply voltage so one stage is okay for that. I have run the simulation in LTspice and it works.



The problem in cadence simulation is that the DC bulk voltage Vb of -I5V I apply somehow leaks onto the output Cinv. There should not be a DC path from bulk to drain/source of the mosfet so its quite perplexing
Now I see your plan is to create opposite polarity of incoming supply. I find I can try to hook up mosfets that conduct via auto-bias, however the body diode conducts at the wrong point in the cycle (reducing output amplitude), or else the mosfet must rely on the body diode to conduct at the proper point in the cycle.

A similar problem comes up when trying to make a full-H-bridge abruptly switch current direction in an inductor.

BJT's are likely a path to a solution in your circuit. Or else diodes are easy to use in strategic locations. The flying capacitor polarity-inverter resembles this handy circuit useful to do the same thing. The full-H-bridge method only needs to have transistors in place of the diodes.

neg fm positive polarity inverter  half-bridge then diode arrangement.png

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to