Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

MOS resistor switch for controlling capacitor

Junus2012

Advanced Member level 5
Joined
Jan 9, 2012
Messages
1,552
Helped
47
Reputation
98
Reaction score
53
Trophy points
1,328
Location
Italy
Activity points
15,235
Hello,

I am using MOS switch for controlling bank of capacitors.

The capacitor bank is a binary weighted array start from 50 fF, 100fF, 200 fF, 400 fF, 80 fF, 1.6 pF,

These capacitor represent the compensation capacitor for my op-amp toward bulding programmable bandwidth amplifier.

Coming to the switch size, what is the rule for sizing it?

I have read that ratio should be high enough to achieve the current phase of a capacitor in the range of -90 ° plus minus 1°, is that true? and how can I simulate it?

this means for every capacitor value there must be different size switch depending on the controlled capacitor size

Thank you in advance for your help

Regards
 
You can run the AC analysis simulation in P-SPICE. This will calculate the frequency response of the circuit. This will allow you to observe the phase shift of the current through the capacitor bank. During the simulation process, you can vary the dimensions of the MOS switch, such as the width-to-length ratio (W/L), to determine its optimal size.
 
You can have a "switch and capacitor" unit for say 50fF.
Then you use multiples of them to get the rest of them.
This way all the RC time constants remain the same since the the switches come in parallel and the capacitors add up.
The above is basically a capacitor DAC. You can find structures of them online in the context of CAPDAC SAR ADCs.

With regards to the sizing, you just have to ensure that the worst case switch resistance does not screw up your compensation by too much. That is, you are still stable within your specifications.

Of course worst case switch resistance would be across PVT+MC
 
thanks for the reply,

let start with the small capacitor unit of 50 fF.
Now you suggested that MOS switch resistor should be considered, I agree. However, in order to reduce the switch resistor, this requires to increase the switch ratio, which in turn increase its parasatic capacitor and might be the parasitic of the switch will be dominated over the unit capacitor.
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top