CMOS Comparator design for the following specifications

[mohan_arun]

Hi all

I want to design a comparator [either a two stage or a pre-amp followed by latch topology] for the following spec:
1. Vin = 1- 5V
2. ICMR = 0-5.5V
3. Slew rate = 15V/us
4. Propagation delay: 5ns
5. PSRR =40dB

Any pointers on how I should proceed on deciding which topology is better and how to do sizing?

Thanks

 

[vivekroy]

If you don't know how to get started, start with the simplest topology. A 5 transistors OTA. See where that gets you.

 

[dick_freebird]

Specs seem pretty tight for a 5V technology. Delay spec
needs elaboration (low overdrive, high overdrive input
test condition). Why does VIN spec range differ from
common mode input range when input difference could
be expected to be trivial when you actually care about
things? Why is ICMR expecting 5.5V when you could
expect VDD to be as low as 4.5V, and any ESD protection
would bind up? A product would spec this VDD-relative.
And no Vio spec? For a comparator, that's only the single
most important DC spec.

Of course you can expect no answers from a canned
homework assignment, most likely. But these are aspects
worth documenting as you proceed, "show work" style.

VIn range sets your front end choice to NMOS pair
(PMOS could be cut off, R-R input probably is more
elaborate that expected). From there it's pretty much
geometries and currents.

Clocked styles let you build in autozero.

 

[mohan_arun]

Thanks for the reply.

My understanding is that the psrr spec would decide the gain needed by the preamplifier, and the delay spec would tell me the bandwidth required. Is this understanding accurate?

 

[D.A.(Tony)Stewart]

study datasheets then make changes

https://www.analog.com/media/en/technical-documentation/data-sheets/MAX917-MAX920.pdf