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Synthesising design with memory macros

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miho

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memory macro + design compiler

Hi,

I'd like to synthesize a design which includes memory macros which were generated by a memory compiler for our target library and are available as .vhdl for simulation and also .lib, .db (compiled them myself), .lef, and and some other files.

My goal is to synthesize the whole design including memories and obtain data on timing, area, power, etc. Including the memory is important for me since I want to annotate switching activity with actual data in the memories to get accurate power estimates.

The problem with the memory macros is that they, although they are fixed in size, width etc. contain lots of generics of type real or VitalDelayType which is not suported by the design compiler.

What should I do about this. Is my approach sensible at all?

Thanks for any hints.
 

the_penetrator

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The VITAL models are only for post-synthesis simulation (or post-PnR).

In Leonardo i use, it is possible (but more tricky than DC i suppose) to copy the library file for the memory component to the library dir. It is not the same file as for the standard cell library.

Then load the library for the component from your synthesis script.

It should be similar for DC with .lib files.

the_penetrator©
 

zyphor

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using memory compiler to generate .db file for dc.
 

aramis

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miho said:
Hi,

I'd like to synthesize a design which includes memory macros which were generated by a memory compiler for our target library and are available as .vhdl for simulation and also .lib, .db (compiled them myself), .lef, and and some other files.

My goal is to synthesize the whole design including memories and obtain data on timing, area, power, etc. Including the memory is important for me since I want to annotate switching activity with actual data in the memories to get accurate power estimates.

The problem with the memory macros is that they, although they are fixed in size, width etc. contain lots of generics of type real or VitalDelayType which is not suported by the design compiler.

What should I do about this. Is my approach sensible at all?

Thanks for any hints.

I used to have the question about the memory macro.
There is no need to synthesis the memory macro, just put the lib/db file into your design compiler library path and link with it.



please see
https://www.elektroda.pl/eboard/searchtopic48320-.html
 

jkfoo

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In DC, the memory instantiated in the VHDL file will be treated as black box, do not read the behavorial model of the memory in DC, as they will not be recognized and synthesized. The timing arcs and area are defined in the .lib/.db, you will be able to performed pre-layout timing verification with the memory(during synthesis and STA). As for power, some memory compiler is able to generate datasheet and indicate the power consumption under certain conditions, so you are able to do your own estimation.
 

miho

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@aramis: thanks, that solved my problem. I meanwhile had figured it myself sortof by chance. Thanks anyway!
 

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