Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

synopsys removing unconnected ports

Status
Not open for further replies.

peen1

Member level 2
Joined
Nov 2, 2004
Messages
47
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
495
deleting top-level ports

Hi All,
I am trying to do synthesis and synopsys is removing un-connected output ports. This gives problems when I do simulations. Like the simulation tool looks for Q and Q-bar in a flop.

How do I tell DC not to remove un-connected ports? Can DC insert some wire in the port and leave it?

Thanks
 

aravind

Advanced Member level 1
Joined
Jun 29, 2004
Messages
487
Helped
45
Reputation
94
Reaction score
18
Trophy points
1,298
Location
india
Activity points
3,597
removing unconnected flop

u cant do it. basically tools do optimation from I/O ports. it is see whether all outputs connect to all output ports if not it will remove all cells connected on the wire /net (hanging).
this basic algorithm in all CAD tools.
but u can try without boudary optimazation.
but i dont know the tools will have such command .
because it is first pause optimization.
 

peen1

Member level 2
Joined
Nov 2, 2004
Messages
47
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
495
remove unconnected

Thanks Arvind,

The issue is that we are trying to convert a netlist file from one asic technology to another. In the old netlist, the unconnected ports had wires inserted in them. When DC maps the old netlist to new asic cells, It starts removing these hanging ports.

I am trying to figure out why DC did not optomize out the hanging ports in the old technology netlist.
 

aravind

Advanced Member level 1
Joined
Jun 29, 2004
Messages
487
Helped
45
Reputation
94
Reaction score
18
Trophy points
1,298
Location
india
Activity points
3,597
ports old technology

then u should give synthezie optimize level 0
same as elaborate stage.
simply import design and eleaborate and synthesize in level 0.
 

ami

Member level 3
Joined
Apr 28, 2005
Messages
62
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Location
VN
Activity points
1,952
synopsis unconnected

try this,
Code:
ungroup_keep_original_design = true
rgrds
 

jjww110

Full Member level 5
Joined
Apr 19, 2005
Messages
258
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Location
china
Activity points
2,933
synopsys unconnected

u should modify netlist
 

eda_wiz

Advanced Member level 2
Joined
Nov 7, 2001
Messages
654
Helped
57
Reputation
114
Reaction score
29
Trophy points
1,308
Activity points
6,195
verilogout_show_unconnected_pins

peen,

Code:
set verilogout_show_unconnected_pins true
just include this line in ur script .. u r done
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top