synopsys removing unconnected ports

[peen1]

deleting top-level ports

Hi All,
I am trying to do synthesis and synopsys is removing un-connected output ports. This gives problems when I do simulations. Like the simulation tool looks for Q and Q-bar in a flop.

How do I tell DC not to remove un-connected ports? Can DC insert some wire in the port and leave it?

Thanks

 

[aravind]

removing unconnected flop

u cant do it. basically tools do optimation from I/O ports. it is see whether all outputs connect to all output ports if not it will remove all cells connected on the wire /net (hanging).
this basic algorithm in all CAD tools.
but u can try without boudary optimazation.
but i dont know the tools will have such command .
because it is first pause optimization.

 

[peen1]

remove unconnected

Thanks Arvind,

The issue is that we are trying to convert a netlist file from one asic technology to another. In the old netlist, the unconnected ports had wires inserted in them. When DC maps the old netlist to new asic cells, It starts removing these hanging ports.

I am trying to figure out why DC did not optomize out the hanging ports in the old technology netlist.

 

[aravind]

ports old technology

then u should give synthezie optimize level 0
same as elaborate stage.
simply import design and eleaborate and synthesize in level 0.

 

[ami]

synopsis unconnected

try this,

ungroup_keep_original_design = true

rgrds

 

[jjww110]

synopsys unconnected

u should modify netlist

 

[eda_wiz]

verilogout_show_unconnected_pins

peen,

set verilogout_show_unconnected_pins true

just include this line in ur script .. u r done