[Synopsys] ICC vs Design Compiler

[ivlsi]

Hi All,

I'm familiar with Synopsys Design Compiler. How ICC is different? Does it just use P&R information instead of WLM? How is the flow different for the block-level synthesis?

Thank you!

 

[ro9ty]

Hi,

DC is a synthesis tool which means it does logic mapping and optimization. ICC is a PnR tool i.e Placement and routing tool. It has a vast use. You can start with WLM but after CTS and routing, you have to extract SPEF (parasitic information) and back-annotate it to compute your timing and voltage. You can also use DC in topo mode wherein you can feed the SPEF and floor plan information and the DC can do a far better optimization in saving area and congestion, but ultimately you will have to place it in ICC and visually check for the congestion hot-spots etc... In fact at a later stage every bit of input - timing, voltage, IR, PV, LEC - every feedback comes to the PnR guy, even the fixes and he decides where and how to implement the fixes. Ex. if there is a timing violation and the Timing guy asks to add a buffer on X net. The PnR guy checks if adding a buffer in that area is possible or is there a blockage there or huge congestion.
ICC is the heart of PnR.