mathi
Junior Member level 2
force design compiler
Hi all,
I want to know if there is a way of preventing design compiler from removing used pins when writing the gate-level netlist? My library has flip-flops with inputs and outputs declared as follows DFF(CLK, D, Q, QN). When I save the netlist using desing compiler it ignores all the unused QN output. This causes problem during verification. Is there a way I can force design compiler to keep the unused pins?
Hi all,
I want to know if there is a way of preventing design compiler from removing used pins when writing the gate-level netlist? My library has flip-flops with inputs and outputs declared as follows DFF(CLK, D, Q, QN). When I save the netlist using desing compiler it ignores all the unused QN output. This causes problem during verification. Is there a way I can force design compiler to keep the unused pins?