synopsys design compiler

[mathi]

force design compiler

Hi all,

I want to know if there is a way of preventing design compiler from removing used pins when writing the gate-level netlist? My library has flip-flops with inputs and outputs declared as follows DFF(CLK, D, Q, QN). When I save the netlist using desing compiler it ignores all the unused QN output. This causes problem during verification. Is there a way I can force design compiler to keep the unused pins?

 

[gong.kidd]

U can add some parameter when simulating on simulation software such as NC

 

[Atre]

Hello,

You need to set a variable before writing out your netlist: verilogout_show_unconnected_pins

Good luck!

Hi all,

I want to know if there is a way of preventing design compiler from removing used pins when writing the gate-level netlist? My library has flip-flops with inputs and outputs declared as follows DFF(CLK, D, Q, QN). When I save the netlist using desing compiler it ignores all the unused QN output. This causes problem during verification. Is there a way I can force design compiler to keep the unused pins?

 

[rakesh_aadhimoolam]

There is a lot of free downloadable information abt DC........in this sub-forum(ASIC)

The date hold backs to 28 SEP 2004....(page may be 118)


Just go through it.........


good luck....................

 

[mathi]

Thanks Atre, I got it work.